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september 2013 doc id 018513 rev 2 1/32 1 VND5T100AJ-E double channel high-side driver with analog current sense for 24 v automotive applications features general ? very low standby current ? 3.0 v cmos compatible input ? optimized electromagnetic emission ? very low electromag netic susceptibility ? compliance with european directive 2002/95/ec ? fault reset standby pin (fr_stby) diagnostic functions ? proportional load current sense ? high current sense precision for wide range currents ? off-state open-load detection ? output short to v cc detection ? overload and short to ground latch-off ? thermal shutdown latch-off ? very low current sense leakage protection ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self limiting of fast thermal transients ? protection against loss of ground and loss of v cc ? thermal shutdown ? electrostatic discharge protection application all types of resistive, inductive and capacitive loads description the VND5T100AJ-E is a monolithic device made using stmicroelectronics? vipower? technology, intended fo r driving resistive or inductive loads with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes. this device integrates an analog current sense which delivers a current proportional to the load current. fault conditions such as overload, overtemperature or short to v cc are reported via the current sense pin. output current limitation protects the device in overload condition. the device latches off in case of overload or thermal shutdown. the device is reset by a low level pass on the fault reset standby pin. a permanent low level on the inputs and fault reset standby pin disables all outputs and sets the device in standby mode. max transient supply voltage v cc 58 v operating voltage range v cc 8 to 36 v typ on-state resistance (per ch.) r on 100 m ? current limitation (typ) i lim 22 a off-state supply current i s 2a (1) 1. typical value with all loads connected. powersso-12 www.st.com
contents VND5T100AJ-E 2/32 doc id 018513 rev 2 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21 3.1.1 solution 1: resistor in the ground line (rgnd only) . . . . . . . . . . . . . . . . 21 3.1.2 solution 2: diode (dgnd) in the ground line . . . . . . . . . . . . . . . . . . . . . 22 3.2 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 mcu i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 maximum demagnetization energy (v cc = 24 v) . . . . . . . . . . . . . . . . . . . 23 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 powersso-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 powersso-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VND5T100AJ-E list of tables doc id 018513 rev 2 3/32 list of tables table 1. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. current sense (8 v < v cc < 36 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 10. open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 11. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 14. electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 15. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16. powersso-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
list of figures VND5T100AJ-E 4/32 doc id 018513 rev 2 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. t standby definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. t reset definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. output stuck to v cc detection delay time at frstby activation . . . . . . . . . . . . . . . . . . . . 15 figure 10. delay response time between rising edge of output current and rising edge of current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 16. input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 17. input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 18. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 19. on-state resistance vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 20. on-state resistance vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 21. i limh vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 22. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 23. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 24. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 25. maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 26. powersso-12 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 27. rthj-amb vs pcb copper area in open box free air condition (one channel on) . . . . . . . . 24 figure 28. powersso-12 thermal impedance junction ambient single pulse (one channel on). . . . . 25 figure 29. thermal fitting model of a double channel hsd in powersso-12 . . . . . . . . . . . . . . . . . . . 25 figure 30. powersso-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 31. powersso-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 32. powersso-12 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VND5T100AJ-E block diagram and pin description doc id 018513 rev 2 5/32 1 block diagram and pin description figure 1. block diagram table 1. pin function name function v cc battery connection outn power output gnd ground connection inn voltage controlled input pin with hysteres is, cmos compatible. controls output switch state csn analog current sense pin, delivers a cu rrent proportional to the load current fr_stby in case of latch-off for ot/overcurrent condition, a low pulse on the fr_stby pin is needed to reset the channel. the device enters in standby mode if all inputs and the fr_stby pin are low. &rqwuro 'ldjqrvwlf 9 && &+ /2*,& '5,9(5 9 21 /lplwdwlrq &xuuhqw /lplwdwlrq 3rzhu &odps 2yhu 7hpshudwxuh 8qghuyrowdjh &+ 29(5/2$'3527(&7,21 $&7,9(32:(5/,0,7$7,21 ,1 ,1 &6 &6 )5b6we\ *1' 287 287 6ljqdo&odps *$3*&)7 &xuuhqw 6hqvh 9 6(16(+ &rqwuro 'ldjqrvwlf 2))vwdwh 2shqordg
block diagram and pin description VND5T100AJ-E 6/32 doc id 018513 rev 2 figure 2. configuration diagram (top view) table 2. suggested connections for unused and not connected pins connection / pin current sense n.c. output input fr_stby floating not allowed x x x x to ground through 10 k ?? resistor x not allowed through 10 k ?? resistor through 10 k ?? resistor 7$% 9 && 3rzhu662 *$3*&)7 9 && 9 && 287 287 287 287 *1' ,1 &6 )5b67%< ,1 &6
VND5T100AJ-E electrical specifications doc id 018513 rev 2 7/32 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings stressing the device above the ratings listed in ta b l e 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to the conditions reported in this section for extended periods may affect device reliability. refer also to the stmicroelectronics? sure progra m and other relevant quality documents. , 6 , *1' 9 && 287q , 287q , 6(16(q ,1q , ,1q *1' )5b6we\ 9 )5b6we\ ,1q &6q 9 6(16(q 9 287q 9 )q , )5b6we\ 1rwh9 )q 9 287q 9 && gxulqjuhyhuvhedwwhu\frqglwlrq 9 && *$3*&)7 table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 58 v -v cc reverse dc supply voltage 0.3 v -i gnd dc reverse ground pin current 200 ma i out dc output current internally limited a -i out reverse dc output current 20 a i in dc input current -1 to 10 ma i fr_stby fault reset standby dc input current -1 to 1.5 ma -i csense dc reverse cs pin current 200 ma v csense current sense maximum voltage v cc - 58 to +v cc v
electrical specifications VND5T100AJ-E 8/32 doc id 018513 rev 2 2.2 thermal data e max maximum switching energy (l = 1.9 mh; v bat =32 v; t jstart =150c; i out = i liml (typ)) 70 mj v esd electrostatic discharge (human body model: r = 1.5 k ?? c = 100 pf) ? input ? current sense ?fr_stby ?output ?v cc 4000 2000 4000 5000 5000 v v v v v v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 c l smax maximum stray inductance in short circuit r l = 300 m ? , v bat =32v, t jstart = 150 c, i out =i limhmax 40 h table 3. absolute maximum ratings (continued) symbol parameter value unit table 4. thermal data symbol parameter maximum value unit r thj-case thermal resistance junction-case (with one channel on) 3 c/w r thj-amb thermal resistance junction-ambient see figure 27 c/w
VND5T100AJ-E electrical specifications doc id 018513 rev 2 9/32 2.3 electrical characteristics 8v electrical specifications VND5T100AJ-E 10/32 doc id 018513 rev 2 figure 4. t standby definition table 7. logic inputs symbol parameter test conditions min. typ. max. unit v il input low level voltage 0.9 v i il low level input current v in =0.9v 1 a v ih input high level voltage 2.1 v i ih high level input current v in = 2.1 v 10 a v i(hyst) input hysteresis voltage 0.25 v v icl input clamp voltage i in = 1 ma 5.5 7 v i in = -1 ma -0.7 v v fr_stby_l fault_reset_standby low level voltage 0.9 v i fr_stby_l low level fault_reset_standby current v fr_stby = 0.9 v 1 a v fr_stby_h fault_reset_standby high level voltage 2.1 v i fr_stby_h high level fault_reset_standby current v fr_stby = 2.1 v 10 a v fr_stby (hyst) fault_reset_standby hysteresis voltage 0.25 v v fr_stby_cl fault_reset_standby clamp voltage i fr_stby = 15 ma (t < 10 ms) 11 15 v i fr_stby = -1 ma -0.7 v t reset overload latch-off reset time see figure 4 224s t stby standby delay see figure 5 120 1200 s w vwe\ w vwe\ )5b6wge\ ,1387q ,*1' *$3*&)7
VND5T100AJ-E electrical specifications doc id 018513 rev 2 11/32 figure 5. t reset definition table 8. protections and diagnostics symbol parameter test conditions min. typ. max. unit i limh dc short circuit current v cc = 24 v 5v electrical specifications VND5T100AJ-E 12/32 doc id 018513 rev 2 table 9. current sense (8 v < v cc <36v) symbol parameter test conditions min. typ. max. unit k 1 i out /i sense i out = 350 ma; v sense = 1 v; t j = -40 c...150 c t j = 25 c...150 c 930 1050 1547 1547 2185 2020 dk 1 /k 1 (1) current sense ratio drift i out = 350 ma; v sense = 1 v; t j = -40 c to 150 c -15 15 % k 2 i out /i sense i out = 0.8 a; v sense = 2 v; t j = -40 c...150 c t j = 25 c...150 c 1225 1310 1528 1528 1835 1745 dk 2 /k 2 (1) current sense ratio drift i out = 0.8 a; v sense = 2 v; t j = -40 c to 150 c -12 12 % k 3 i out /i sense i out = 1.5 a; v sense = 2 v; t j = -40 c...150 c t j = 25 c...150 c 1340 1405 1525 1525 1715 1655 dk 3 /k 3 (1) current sense ratio drift i out = 1.5 a; v sense = 2 v; t j = -40 c to 150 c -8 8 % k 4 i out /i sense i out = 6 a; v sense = 4 v; t j = -40 c...150 c t j = 25 c...150 c 1450 1475 1522 1522 1600 1560 dk 4 /k 4 (1) current sense ratio drift i out = 6 a; v sense = 4 v; t j = -40 c to 150 c -5 5 % i sense0 analog sense leakage current i out = 0 a; v sense = 0 v; v in = 0 v; t j = -40 c...150 c v in = 5 v; t j = -40 c...150 c 0 0 1 2 a a v sense max analog sense output voltage i out = 6 a; r sense = 3.9 k ? 5v v senseh analog sense output voltage in fault condition (2) v cc =24v; r sense = 3.9 k ? 7.5 8.5 9.5 v i senseh analog sense output current in fault condition (2) v cc = 24 v; v sense = 5 v 4.9 9 12 ma t dsense2h delay response time from rising edge of input pin v sense < 4 v, 0.07 a < i out <6a i sense =90% of i sense max (see figure 6 ) 100 200 s
VND5T100AJ-E electrical specifications doc id 018513 rev 2 13/32 figure 6. current sense delay characteristics ? t dsen se 2h delay response time between rising edge of output current and rising edge of current sense v sense <4v, i sense = 90 % of i sensemax, i out =90% of i outmax i outmax = 1.5 a (see figure 11 ) 150 s t dsense2l delay response time from falling edge of input pin v sense < 4 v, 0.07 a < i out <6a i sense =10% of i sense max (see figure 6 ) 520s 1. parameter guaranteed by design; it is not tested. 2. fault condition includes: power limitation, overtemperature and op en-load in off-state condition. table 10. open-load detection symbol parameter test conditions min. typ. max. unit v ol open-load off-state voltage detection threshold v in = 0 v; 8 v < v cc <36 v; f r_stby =5v 24v t dstkon output short circuit to v cc detection delay at turn off see figure 6 ; f r_stby =5v 180 1800 s t dfrstk_on output short circuit to v cc detection delay at frstby activation see figure 9 ; input 1,2 = low 50 s i l(off2) off-state output current at v out = 4v v in =0v; v sense =0v; v out rising from 0 v to 4 v; f r_stby =5v -120 0 a t d_vol delay response from output rising edge to v sense rising edge in open-load v out = 4 v; v in = 0 v v sense = 90 % of v senseh r sense = 3.9 k ??? f r_stby =5v 20 s table 9. current sense (8 v < v cc < 36 v) (continued) symbol parameter test conditions min. typ. max. unit 6(16(&855(17 ,1387 /2$'&855(17 w '6(16(+ w '6(16(/ *$3*&)7
electrical specifications VND5T100AJ-E 14/32 doc id 018513 rev 2 figure 7. open-load off-state delay timing figure 8. switching characteristics 9 287 !9 2/ 9 6(16(+ 9 ,1 9 &6 w '67.21 2xwsxwvwxfndw9 && *$3*&)7 9 287 g9 287 gw rq w u w i 7 grii ,1387 w w 7 grq g9 287 gw rii *$3*&)7 w :rq w :rii
VND5T100AJ-E electrical specifications doc id 018513 rev 2 15/32 figure 9. output stuck to v cc detection delay time at frstby activation figure 10. delay response time between ri sing edge of output current and rising edge of current sense w ')567.b21 )5 67%< 9 &6 9 vhqvh+ ,qsxw /rz *$3*&)7 9 ,1 , 287 , 2870$; , 2870$; w w w , 6(16(0$; ?w '6(16(+ , 6(16( , 6(16(0$; *$3*&)7
electrical specifications VND5T100AJ-E 16/32 doc id 018513 rev 2 figure 11. output voltage drop limitation figure 12. device behavior in overload condition 9 21 , 287 7 m ?& 7 m ?& 7 m ?& 9 21 5 21 7 9 && 9 287 $*9 )$8/7b5(6(7 ,1 q 287387 q &6 q 29(5/2$' &+$11(/ q 9 vhqvh+ ryhuordg ryhuordguhvhw ryhuordggldjuhvhw wbuhvhw 287387 q dqg&6 q frqwuroohge\,qq )$8/7b5(6(7iurp?wr?:qrdfwlrqrq&6 q slq ryhuordgodwfkrii,qqkljk:&6 q kljk )$8/7b5(6(7orz$1'7hpsfkdqqhoqryhuordgbuhvhw:ryhuord godwfkuhvhwdiwhuwbuhvhw wr)$8/7b5(6(7orz$1',1 q kljk:wkhupdof\folqj&6 q kljk )$8/7b5(6(7kljk:odwfkriiuhvhwglvdeohg wrryhuordghyhqwdqg)$8/7b5(6(7kljk:odwfkriiqrwkh updof\folqj wrryhuordggldjqrvwlfglvdeohghqdeohge\wkhlqsxw ryhuordgodwfkriiuhvhwe\)$8/7b5(6(7 29(5/2$' wkhupdovkxwgrzq25srzhuolplwdwlrq wbuhvhw *$3*&)7
VND5T100AJ-E electrical specifications doc id 018513 rev 2 17/32 table 11. truth table conditions fault reset standby input output sense standby l l l 0 normal operation x x l h l h 0 nominal overload x x l h l h 0 > nominal overtemperature / short to ground x l h l h h l cycling latched 0 v senseh v senseh undervoltage x x l 0 short to v bat l h x l l h h h h 0 v senseh < nominal open-load off-stat e (with pull-up) l h x l l h h h h 0 v senseh 0 negative output voltage clamp x l negative 0
electrical specifications VND5T100AJ-E 18/32 doc id 018513 rev 2 table 12. electrical transient requirements (part 1) iso 7637-2: 2004(e) test pulse test levels (1) number of pulses or test times burst cycle/pulse repetition time delays and impedance iii iv 1 - 450 v - 600 v 5000 pulses 0.5 s 5 s 1 ms, 50 ? 2a + 37 v + 50 v 5000 pulses 0.2 s 5 s 50 s, 2 ? 3a - 150 v - 200 v 1h 90 ms 100 ms 0.1 s, 50 ? 3b + 150 v + 200 v 1h 90 ms 100 ms 0.1 s, 50 ? 4 - 12 v - 16 v 1 pulse 100 ms, 0.01 ? 5b (2) + 123 v + 174 v 1 pulse 350 ms, 1 ? table 13. electrical transient requirements (part 2) iso 7637-2: 2004(e) test pulse test level results iii iv 1c c 2a c c 3a c c 3b (1) 1. without capacitor between v cc and gnd. ee 3b (2) 2. with 10 nf between v cc and gnd. cc 4c c 5b (3) 3. external load dump clamp, 58 v maximum, referred to ground. cc table 14. electrical transient requirements (part 3) class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
VND5T100AJ-E electrical specifications doc id 018513 rev 2 19/32 2.4 electrical characteristics curves figure 13. off-state output current figure 14. high level input current figure 15. input clamp voltage figure 16. input high level voltage figure 17. input low level voltage figure 18. input hysteresis voltage )loff;u!= 4c;?#= '!0'#&4 /ffstate 6##6 6in6out )ih;u!= 4c;?#= 6in6 '!0'#&4 6icl;6= 4c;?#= )inm ! '!0'#&4 6ih;6= 4c;?#= '!0'#&4 6il;6= 4c;?#= '!0'#&4 6ihyst;6= 4c;?#= '!0'#&4
electrical specifications VND5T100AJ-E 20/32 doc id 018513 rev 2 figure 19. on-state resistance vs t case figure 20. on-state resistance vs v cc figure 21. i limh vs t case figure 22. turn-on voltage slope figure 23. turn-off voltage slope 5rq > p 2k p @ 7f>?&@ ,rxw $ 9ff 9 ("1($'5 2on ; m /h m = 6cc;6= 4c?# 4c?# 4c?# 4c ?# '!0'#&4 )lim h;!= 4c;?#= 6cc6 '!0'#&4 d6outdt /n;6us= 4c;?#= 6cc6 2l '!0'#&4 d6outdt /ff;6us= 4c;?#= 6cc6 2l '!0'#&4
VND5T100AJ-E application information doc id 018513 rev 2 21/32 3 application information figure 24. application schematic 3.1 gnd protection networ k against reverse battery 3.1.1 solution 1: resist or in the ground line (r gnd only) this solution can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1. r gnd ? 600 mv / (i s(on)max ). 2. r gnd ???? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. power dissipation in r gnd (when v cc < 0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsds. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not shared by the device ground then the r gnd produces a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift varies depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then st suggests solution 2 is used (see below). 9 && *1' 287 9 )5b6we\ ,1 5 surw ' og 5 6(16( &6 0&8 & h[w 5 surw 5 surw *$3*&)7 9 *1' ' *1'
application information VND5T100AJ-E 22/32 doc id 018513 rev 2 3.1.2 solution 2: diode (d gnd ) in the ground line a resistor (r gnd =4.7k ??? should be inserted in parallel to d gnd if the device drives an inductive load. this small signal diode can be safely shared amongst several different hsds. also in this case, the presence of the ground network produces a shift ( ? 600 mv) in the input threshold and in the status output values, if the microprocessor ground is not common to the device ground. this shift not varies if more than one hsd shares the same diode/resistor network. 3.2 load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds to v cc max dc rating. the same applies if the device is subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/2 table. 3.3 mcu ? i/os protection if a ground protection network is used and negative transient are present on the v cc line, the control pins are pulled negative. st suggests that a resistor (r prot ) be inserted in line to prevent the microcontroller i/o pins to latch-up. the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of microcontroller i/os. -v ccpeak /i latchup ? r prot ? (v oh ? c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = -600 v and i latchup ? 20 ma; v oh ? c ? 4.5 v 30 k ? ? r prot ? 180 k ? . recommended r prot value is 60 k ??
VND5T100AJ-E application information doc id 018513 rev 2 23/32 3.4 maximum demagnetization energy (v cc = 24 v) figure 25. maximum turn-off current versus inductance c: t jstart = 125c repetitive pulse a: t jstart = 150c single pulse b: t jstart = 100c repetitive pulse demagnetization demagnetization demagnetization t v in , i l 0.1 1 10 1 10 100 1000 l (mh) i (a) a b c note: values are generated with r l =0 ? . in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves a and b.
package and pcb thermal data VND5T100AJ-E 24/32 doc id 018513 rev 2 4 package and pcb thermal data 4.1 powersso-12 thermal data figure 26. powersso-12 pc board figure 27. r thj-amb vs pcb copper area in open box fr ee air condition (one channel on) . *$3*&)7 note: layout condition of r th and z th measurements (board finish thickness 1.6 mm +/- 10 %; board double layer; board dimension 77 mm x 86 mm; board material fr4; cu thicknes s 0.070 mm (front and back side); thermal vias separation 1.2 mm; thermal via diameter 0.3 mm +/- 0.08 mm; cu thickness on vias 0.025 mm; footprint dimension 4.1 mm x 6.5 mm) 30 35 40 45 50 55 60 65 0246810 rthjamb rthjamb gapgcft000124
VND5T100AJ-E package and pcb thermal data doc id 018513 rev 2 25/32 figure 28. powersso-12 thermal impedance junction ambient single pulse (one channel on) figure 29. thermal fitting model of a double channel hsd in powersso-12 equation 1: pulse calculation formula 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 zth (c/w) time (s) cu=8 cm2 cu=2 cm2 cu=foot print gapgc ft000125 *$3*&)7 note: the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. z th ? r th ? z thtp 1 ? ? ?? + ? = where ? t p t ? =
package and pcb thermal data VND5T100AJ-E 26/32 doc id 018513 rev 2 table 15. thermal parameters area/island (cm 2 )footprint28 r1 = r7 (c/w) 0.8 r2 = r8 (c/w) 1.5 r3 (c/w) 3 r4 (c/w) 8 8 7 r5 (c/w) 22 15 10 r6 (c/w) 26 20 15 c1 = c7 (w.s/c) 0.0008 c2 = c8 (w.s/c) 0.005 c3 (w.s/c) 0.05 c4 (w.s/c) 0.2 0.1 0.1 c5 (w.s/c) 0.27 0.8 1 c6 (w.s/c) 3 6 9
VND5T100AJ-E package and packing information doc id 018513 rev 2 27/32 5 package and packing information 5.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 5.2 powersso-12 mechanical data figure 30. powersso-12 package dimensions *$3*&)7
package and packing information VND5T100AJ-E 28/32 doc id 018513 rev 2 table 16. powersso-12 mechanical data symbol millimeters min. typ. max. a 1.250 - 1.620 a1 0.000 - 0.100 a2 1.100 - 1.650 b 0.230 - 0.410 c 0.190 - 0.250 d 4.800 - 5.000 e 3.800 - 4.000 e - 0.800 - h 5.800 - 6.200 h 0.250 - 0.500 l 0.400 - 1.270 k0-8 x 2.200 - 2.800 y 2.900 - 3.500 ddd - - 0.100
VND5T100AJ-E package and packing information doc id 018513 rev 2 29/32 5.3 packing information figure 31. powersso-12 tube shipment (no suffix) figure 32. powersso-12 tape and reel shipment (suffix ?tr?) b a c ga p gcft000123 all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a1.85 b6.75 c ( 0.1) 0.6 base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.05) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.1) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
order code VND5T100AJ-E 30/32 doc id 018513 rev 2 6 order code table 17. device summary package order codes tube tape and reel powersso-12 vnd5t100 aj-e vnd5t100ajtr-e
VND5T100AJ-E revision history doc id 018513 rev 2 31/32 7 revision history table 18. document revision history date revision changes 08-mar-2011 1 initial release. 25-sep-2013 2 disclaimer updated.
VND5T100AJ-E 32/32 doc id 018513 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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